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Silicon Labs /BGM240PB32VNN /VDAC1_S /CH1CFG

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Interpret as CH1CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CONTINUOUS)CONVMODE 0 (HIGHPOWER)POWERMODE 0 (NONE)TRIGMODE 0 (NONE)REFRESHSOURCE 0FIFODVL 0 (HIGHCAPLOADEN)HIGHCAPLOADEN 0 (KEEPWARM)KEEPWARM

REFRESHSOURCE=NONE, TRIGMODE=NONE, POWERMODE=HIGHPOWER, CONVMODE=CONTINUOUS

Description

No Description

Fields

CONVMODE

Channel 1 Conversion Mode

0 (CONTINUOUS): DAC channel 1 is set in continuous mode

1 (SAMPLEOFF): DAC channel 1 is set in sample/shut off mode
POWERMODE

Channel 1 Power Mode

0 (HIGHPOWER): Default is High Power Mode

1 (LOWPOWER): Set this bit for Low Power Mode
TRIGMODE

Channel 1 Trigger Mode

0 (NONE): No Conversion Trigger Source Selected for Channel 1

1 (SW): Channel 1 is triggered by Channel 1 FIFO (CH1F) write

2 (SYNCPRS): Channel 1 is triggered by Sync PRS input.PRS Trigger should have the same clock group as VDAC.

4 (INTERNALTIMER): Channel 1 is triggered by Internal Timer Overflow

5 (ASYNCPRS): Channel 1 is triggered by Async PRS input
REFRESHSOURCE

Channel 1 Refresh Source

0 (NONE): No Refresh Source Selected

1 (REFRESHTIMER): CH1 Refresh Triggered by Refresh Timer Overflow

2 (SYNCPRS): CH1 Refresh Triggered by Sync PRS. PRS Trigger should have the same clock group as VDAC.

3 (ASYNCPRS): CH1 Refresh Triggered by Async PRS
FIFODVL

Channel 1 FIFO Low Watermark
HIGHCAPLOADEN

Channel 1 High Cap Load Mode Enable
KEEPWARM

Channel 1 Keepwarm Mode Enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data